Show HN: Auto-Architecture: Karpathy's Loop, Pointed at a CPU
What happens when you take an autonomous research loop out of its comfort zone and aim it at a domain it has no business being good at? Andrej Karpathy's autoresearch showed that a coding agent, given two days and a single-GPU nanochat, finds 20 training-time optimizations on its own. The recipe is general — propose, implement, measure, keep the wins — but the demonstration was inside the agent's home turf: Python, gradient descent, well-known knobs.
I wanted to know if it generalized. So I pointed it at a CPU.
auto-arch-tournament is a 5-stage in-order RV32IM core in SystemVerilog — the textbook pipeline you'd write in a graduate architecture class. No caches, no branch predictor, no multi-issue on day one. Those are research-loop hypotheses, not features.
The orchestrator is hardcoded. The LLM never edits it. Each round, three slots run in parallel:
A diversity rotation forces each slot to pick a different category ( micro_opt | structural | predictor | memory | extension ) so the agent doesn't fixate on one idea.
Baseline locked at the same methodology VexRiscv publishes — full no cache, 2K data, -O3 , ~22% bus backpressure — at 2.23 CoreMark/MHz, 301 iter/s . The human benchmark is VexRiscv's published 2.57 CoreMark/MHz @ 144 MHz.