RISC-V is now officially supported by CPython
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Over the last few months, I’ve been working on improving CPython’s support for the RISC-V architecture, and I’m thrilled to announce that RISC-V is now officially supported by CPython as a tier 3 platform! 🎉 🚀
RISC-V is an open instruction set architecture (ISA) . Importantly, unlike proprietary instruction sets (such as x86 and ARM), it is developed as an open standard and can be implemented by anyone.
Its ecosystem has grown considerably in recent years and is projected to quadruple by 2032 . With that growth, it’s increasingly important that Python works reliably on these platforms.
This would not have been possible without community contributions. RISC-V support in CPython has developed over time with people testing on real hardware, fixing architecture-specific issues, improving build support, reporting bugs, and reviewing patches. That work is what has brought the platform to the point where it could be added to PEP 11 .
A particularly important part of this has been having reliable, ongoing testing on real RISC-V hardware. I’d like to thank the RISE Project for their support. RISE has kindly provided several RISC-V machines for CPython, giving us buildbots for testing as well as debugging architecture-specific issues.
I’d especially like to thank Ludovic Henry from the RISE Project, Furkan Onder , and Emma Smith , along with the many others who have contributed. Additionally, I’m personally grateful for the Sovereign Tech Agency , which through their amazing fellowship supported my work on this.